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3965
PRELIMINARY DATASHEET - 5/15/01 (Subject to change without notice)
DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER
Designed for Pulse Width Modulated (PWM) current control of low voltage stepper motors, the A3965S is capable of output currents to 500 mA and operating voltages to 20 V. The A3965 is particularly attractive for low power or battery operated motors where minimal power consumption is desired. A SLEEP mode disables all circuitry and typically draws less than 1A supply current from motor and logic supply. During operation the fixed frequency ON pulses of each H-bridge are 180 degrees out of phase to minimize the peak demand required of the motor supply allowing savings in size and cost of external power supply components. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a stepper motor with externally applied PWM control signals. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of VDD and charge pump, and crossover current protection. Special power up sequencing is not required. The 3965 is supplied in a choice of two power packages, The A3965 is supplied in a 24-lead plastic SOIC with a copper batwing tab (suffix `LB').
ABSOLUTE MAXIMUM RATINGS at TA = +25C
Load Supply Voltage, VBB ..........................20 V Output Current, IOUT............................ 500 mA* Logic Supply Voltage, VDD ..........................7.0 V Logic Input Voltage Range, VIN ......................-0.3 V to VDD + 0.3 V (tW<30ns) ..................-1.0V to VDD +1V Sense Voltage, VSENSE ..................................0.5 V Reference Voltage, VREF .................................3 V Package Power Dissipation (TA = +25C), PD A3965SLB........................... 50C/W** Operating Temperature Range, TA ................................ -20C to +85C Junction Temperature, TJ ......................... +150C Storage Temperature Range, TS............................... -55C to +150C
* Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. *Measured with 062" thick FR4, two sided PCB with 1 sq inch copper area.
FEATURES
500 mA, 20 V Output Rating 2.85 to 5.5V Logic Supply Operation Sleep Mode for Minimum Power Consumption Fixed Frequency PWM Offset On Pulses to Minimize Peak Supply Transient Currents Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection
3965 DMOS Dual Full Bridge PWM Motor Driver
Functional Block Diagram
.22uf .22uf VREG CP2 CP1
VDD
BANDGAP
VBB
DMOS H-BRIDGE
VCP
OUT1A
SLEEP
OUT1B
PHASE2
PHASE1
ENABLE1
CONTROL LOGIC
SENSE1
ENABLE2
GATE DRIVE
DMOS H-BRIDGE
VBB
OSC RC
OUT2A
OUT2B S SENSE2 REF2 1/6 Q
R
S SENSE1 REF1 1/6
Q
R
SENSE2 .1uF
GROUND
.22uf
UVLO AND FAULT DETECT
REGULATOR
CHARGE PUMP
VCP
+ + -
3965 DMOS Dual Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 20 V, VDD = 3.0 V, VSENSE = 0.5 V, fPWM < 50KHz (unless noted otherwise)
Limits Characteristics Output Drivers
Load Supply Voltage Range VBB Operating, IOUT = 500 mA During Sleep Mode Output Leakage Current IDSS VOUT = VBB VOUT = 0 V Output On Resistance RDSON Source Driver, IOUT = -500 mA Sink Driver, IOUT = 500 mA Source Driver, IOUT = -500 mA; VBB=6V Sink Driver, IOUT = 500 mA, VBB=6V Body Diode Forward Voltage VF Source Diode, IF = -500 mA Sink Diode, IF = 500mA Motor Supply Current IBB fPWM < 50 kHz Charge Pump On, Outputs Disabled Sleep Mode Logic Supply Current IDD fPWM < 50 kHz Outputs Off Sleep Mode (Inputs below .5V) - - - - - 6 0 - - - - <1.0 <-1.0 1.2 .75 1.3 .85 1 1 3.5 1.5 - 1.9 1.8 <1 - 20 20 20 -20 1.35 .9 1.5 1.0 - - 7 3 10 4 3.6 10 V V A A V V mA mA uA mA mA A
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Control Logic
Logic Supply Voltage Range Logic Input Voltage VDD VIN(1) VIN(0) Logic Input Current IIN(1) IIN(0) VIN = VDD*.7 VIN = VDD*.3 -20 -20 Operating 2.85 VDD*.7 - - <1.0 <1.0 VDD*.3 20 20 5.5 V V V A A
3965 DMOS Dual Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 20V, VDD = 3.0 V, VSENSE = 0.5 V (unless noted otherwise)
Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units
Control Logic
Reference Input Current VREF input voltage range Reference Divider Ratio GM Error IREF VREF VREF/VS VERR (Note 3) Propagation Delay tPD VREF = 1.5V VREF = .5V PWM CHANGE TO SOURCE OFF PWM CHANGE TO SINK OFF PWM CHANGE TO SOURCE ON PWM CHANGE TO SINK ON DISABLE TO SOURCE ON DISABLE TO SINK ON tCOD PWM RC Frequency Blank Time Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis fOSC tBLANK TJ TJ Rising VDD 0.05 R = 1000pf, C = 20K R = 1000pf, C = 20K .8 - - -5 -10 - - - - - - 100 100 100 500 500 200 200 400 47.4 1.21 165 15 2.5 0.10 - 2.8 - 1.6 VREF = VDD -1 0 6 5 10 - - - - - - 800 % % ns ns ns ns ns ns ns Khz s C C V V 0 1 VDD- .1 A
NOTES: 1. 2. 3.
Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device pin.
VERR =((VREF/6) - VSENSE)/(VREF/6)
3965 DMOS Dual Full Bridge PWM Motor Driver
Functional Description
Sleep Mode. The input pin SLEEP is dedicated to put the device into a minimum current draw mode. All circuits are disabled including the VDD undervoltage monitor. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers Current Regulation. Load current is regulated by a
fixed frequency PWM control circuit. When the outputs of the DMOS H-bridge are turned on, current increases in the motor winding until it reaches a value given by: ITRIP = VREF/(6*RSENSE) At the trip point, the sense comparator resets the source enable latch, turning off the source. At this point, load inductance causes the current to recirculate until the end fixed frequency cycle. (see timing diagram) compared to the voltage across the sense resistor to set the value of bridge current that will trip the PWM comparator. The VREF input is a high impedance input and can be connected to VDD, if desired, as well as via resistor divider. Note: When connected to VDD, the VBB voltage must be 1.8V greater than VDD to allow proper headroom for the buffer output.
Fixed Frequency PWM. Selection of an external RC sets the oscillator frequency as follows:
fOSC = 1/ ( 500ns + tBLANK+RTCT))
Blank Time. When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. The blank duration is determined by the time it takes to charge the external RC .38*VDD volts with a 1mA current source.
tBLANK = CT*.38*VDD/ ( 1mA - ( .41*VDD/RT))
VREG. This supply voltage is used to run the sink side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The VREG pin should be decoupled with a 0.22 F capacitor to ground. Charge Pump. The Charge Pump is used to generate a
supply above VBB to drive the source side DMOS gates. A 0.22 uF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 uF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high side DMOS devices. The VCP Voltage is internally monitored and in the case of a fault condition the outputs of the device are disabled.
VREF. The VREF voltage is divided down by 6 and
Thermal protection. Circuitry turns OFF all drivers
when the junction temperature reaches 165C typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15C.
3965 DMOS Dual Full Bridge PWM Motor Driver
Control Logic
Phase X X 0 0 1 1 Enable X 1 0 0 0 0 Sleep 0 1 1 1 1 1 Chopping (Vs>VREF/6) X X 0 1 0 1 OUTA Off Off L L H L OUTB Off Off H L L L Function Sleep Fast Decay Forward Slow Decay Chop Reverse Slow Decay Chop
Typical Full Step Waveforms (Phase = 1)
RC BLANK1 OUT1A IOUT1 VSENSE1
BLANK2 OUT2A IOUT2 VSENSE2
3965 DMOS Dual Full Bridge PWM Motor Driver
Terminal List
Pin Name VREG RC SLEEP VDD OUT1B GND SENSE1 OUT1A ENABLE1 PHASE1 REF1 REF2 PHASE2 ENABLE2 OUT2B SENSE2 GND OUT2A VCP CP2 CP1 VBB Pin Description Regulator decoupling Terminal Analog Input for fixed frequency Logic input for SLEEP mode Logic Supply Voltage DMOS H - Bridge 1 Output B Ground Sense Resistor Terminal for Bridge 2 DMOS H - Bridge 1 Output A Logic Input for Bridge 1 Enable Control Logic Input for Bridge 1 PHASE Control Gm Reference Input Voltage Bridge 2 Gm Reference Input Voltage Bridge 1 Logic Input for Bridge 2 PHASE Control Logic Input for Bridge 2 Enable Control DMOS H - Bridge 2 Output B Sense Resistor Terminal for Bridge 1 Ground DMOS H - Bridge 2 Output A Reservoir Capacitor Terminal Charge Pump Capacitor Terminal Charge Pump Capacitor Terminal Load Supply SOIC 24 1 2 3 4 5 6,7 8 9 10 11 12 13 14 15 16 17 18,19 20 21 22 23 24

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